Principal Design Verification Engineer - QGOV

Qualcomm • San Diego, CA

81d • $192,000 - $288,000

About The Position

The position involves Design Verification with a focus on RTL design in Verilog and System Verilog. The candidate will develop verification methodology to ensure a scalable and portable environment across simulation and emulation. Responsibilities include developing test plans to verify hardware building blocks, design macros, and standard interfaces such as PCIE, DDR, USB, I2C, and SPI. The role requires ownership of end-to-end DV tasks, including coding test benches and test cases, writing assertions, running simulations, and achieving all coverage goals. The candidate will explore innovative DV methodologies to continuously enhance the quality and efficiency of test benches and maintain the emulation environment to collect relevant metrics. This position requires full-time presence in San Diego, five days a week, and applicants must be U.S. citizens eligible for government security clearance.

Requirements

• 10+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture.
• 10+ years of Design Verification, Emulation, and Debug experience with simulation and emulation and prototyping flows.
• Relevant experience of 10+ years in Design/Verification/Implementation.

Nice To Haves

• Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc.
• Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology.
• Good understanding of chip-level functional model building.
• Good understanding of OOP concepts.
• Experience in HVL such as System Verilog, UVM/OVM & System C.
• Knowledge of Behavioral and Structural models and familiarity with simulation environments.
• Experience customizing and debugging make-based build flows and working with Xilinx’s Vivado tools.
• Experience with cm tools such as Git and Gerrit.
• Experience in formal/static verification methodologies.
• Experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs.
• Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog.
• Experience with C/C++ DPI transactors and monitors.
• Develop and maintain emulation environment to collect metrics related to emulation environment.
• Develop environment to run verification test cases, OS boot, performance benchmarks, and other vectors.
• Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test, and debug automations.
• Experience with debugging tools such as JTAG and lab test equipment such as logic analyzers, oscilloscopes, signal generators, etc.
• Experience with GLS, and scripting languages such as Perl, Python.
• Linux OS proficiency.

Responsibilities

• Develop verification methodology ensuring scalable and portable environment across simulation and emulation.
• Develop test plans to verify hardware building blocks, design macros, and standard interfaces (PCIE, DDR, USB, I2C, SPI, etc.).
• Own end-to-end DV tasks from coding test benches and test cases, writing assertions, running simulations, and achieving all coverage goals.
• Explore innovative DV methodologies (formal, simulation, and emulation based) to enhance the quality and efficiency of test benches.
• Develop and maintain emulation environment to collect metrics related to emulation environment.
• Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under care, and debug of test failures.

Benefits

• $192,000.00 - $288,000.00 salary range.
• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants.
• Comprehensive benefits package designed to support success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees