Microsoft-posted 2 months ago
$139,900 - $274,800/Yr
Full-time • Senior
Mountain View, CA
Professional, Scientific, and Technical Services

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for a Principal Design Technical Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment. You will be responsible for developing and maintaining the RTL design flows and methodologies for our cutting edge chip productions. Throughout the program you will be interacting with various teams, including architecture, front end design, verification, DFT and physical design to ensure quality, performance and efficiency of RTL code and tools. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

  • Architect and implement workflows using industry-standard tools and best practices that aid in SOC assembly including RTL handoff between IPs/subsystems/SOC/DFT teams, hierarchy manipulation and feedthrough methodologies, constraint and waiver promotion, specification to design collateral flows etc.
  • Provide guidance and training to the RTL design team on usage of the flows and methodologies
  • Collaborate with RTL design, verification, DFT and Physical design teams to resolve any issues related to RTL code, tools or flows
  • Evaluate new tools, technologies and standards for RTL design and propose improvements and enhancements
  • Document and maintain the RTL design flows and methodologies
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
  • 8+ years of experience delivering successful Front End design using System Verilog or other HDL languages
  • 8+ years expertise in developing and deploying various Front End tools, flows and methodologies such as Lint, CDC, RDC, Synthesis
  • 8+ years of experience in architecting and implementing end to end workflows that aid in RTL development that scale for IP, subsystem and full chip SOC
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
  • 10+ years technical engineering experience
  • 10+ years expertise in developing and deploying various Front End tools, flows and methodologies such as Lint, CDC, RDC and Synthesis
  • 10+ years of experience in architecting and implementing end to end workflows that aid in RTL development that scale for IP, subsystem and full chip SOC
  • Proven track record of architecting and implementing Front End RTL methodologies for multiple SOCs
  • Thorough understanding of end-to-end SOC design cycles and dependencies between design, verification, physical design, DFT teams
  • Proven ability to manage multiple projects simultaneously is a plus
  • Experience working with global design, verification, physical design and product teams
  • Excellent communication skills
  • Industry leading healthcare
  • Educational resources
  • Discounts on products and services
  • Savings and investments
  • Maternity and paternity leave
  • Generous time away
  • Giving programs
  • Opportunities to network and connect
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