Principal ATE Test Engineer

d-Matrix•Santa Clara, CA

12h•Hybrid

About The Position

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI. We are looking for a Principal ATE Test Engineer with proven experience in developing and supporting complex silicon SoC products to lead ATE test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define and implement ATE programs, and own the product from design and initial samples all the way through high volume production ramp. The candidate should have working knowledge of CPU and communication/interface protocols such as PCI-Express (Gen-4/5/6), High Speed D2D, LPDDR (4/5/6), etc. The candidate will also need to work with OSAT to identify and drive test cost reduction, improve both CP and FT yield, identify FT high yield fallout bins, and enhance CP program to minimize such high FT yield fallout bins.

Requirements

Strong academic and technical background in electrical engineering. At minimum, a bachelor’s in EE is required, and a master’s is preferred
12 + years of experience developing & releasing complex SoC/silicon products to high volume manufacturing
Experience with developing high pin count wafer sort probe cards and load boards
Has implemented Scan, at speed Scan, MBist, Serdes loopback
Working knowledge of high-speed protocols like PCIe, LPDDRx, HBM, etc.
Professional attitude with the ability to execute multiple tasks with minimal supervision
Strong team player with good communication skills to work alongside a team of high caliber engineers
Entrepreneurial, open-mind behavior and can-do attitude.
Hands-on experience with high-speed SoC test program/hardware development on the Advantest 93k test platform
Collaboration with the design DFT team to define test strategy and create and own the test plan
Familiar with high-speed and high power load board design techniques
Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality
Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage—AC/DC SCAN, MBIST, DBIst, DSerDes, DDR, D2D, DIMC, and other functional tests
Strong knowledge of lot genealogy from 2DiD barcode down to ECID in eFuse for device serial number, chiplet ID, and die information
Expertise in production testing of high speed SerDes operating at 16 Gbps and higher
Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation, and debug
Experience with lab equipment, including protocol analyzers and oscilloscopes
Experience with data conversion between STDF file format into csv file format using scripts, including extracting ECID reside with eFuse block
Proficiency in modern programming languages such as C/C++ and Python.