Principal ASIC Design Engineer

Credo Technology Group Ltd.-posted about 1 month ago

$180,000 - $210,000/Yr

Full-time • Principal

San Jose, CA

501-1,000 employees

Computer and Electronic Product Manufacturing

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As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and work closely with system teams for chip bring-up and validation.

Design, implement, and debug complex logic blocks.
Integrate complex IPs from internal and external vendors.
Support front-end integration activities such as Lint, CDC, synthesis, and ECO.
Participate in design and code reviews to ensure quality.
Develop functional tests/testbenches and run RTL and gate-level simulations.
Work with verification, DFT, and physical design engineers to achieve successful tape-outs.
Bring up, validate, and debug chip features; collaborate with software, firmware, and systems teams.

BS/MS degree in Electrical Engineering or Computer Science.
10+ years of relevant ASIC design experience.
Strong understanding of digital logic design and complex synchronous/asynchronous interfaces.
Proficiency in Verilog/SystemVerilog RTL design.
Knowledge of synthesis and static timing analysis.
Experience developing testbenches and test cases; familiarity with UVM.
Experience with gate-level simulations, chip bring-up, and validation.
Proven track record of successful production tape-outs.

Expertise in scripting languages (Python, Tcl, Perl, Shell).
Familiarity with DFT methodology and physical design flow.
Hands-on experience with STA and timing closure.
Strong problem-solving and planning skills.
Excellent communication and collaboration abilities.

This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits.

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