Principal ASIC Design Engineer (Starshield)

SpaceX • Irvine, CA

1d

About The Position

Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

Requirements

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 8+ years of experience in RTL implementation and/or FPGA/ASIC development.

Nice To Haves

• Experience solving problems including clock domain crossings and power optimization.
• Experience developing complex ASICs.
• Experience with multicore CPU subsystem design.
• Experience with standard bus protocols (e.g. AXI, AHB, etc.).
• Experience with embedded processors.
• Experience with high speed and low power design techniques.
• Scripting skills (Python, TCL etc.).
• Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
• Ability to work in a dynamic environment with changing needs and requirements.
• Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
• Enjoy being challenged and learning new skills.

Responsibilities

• Design digital ASICs and/or FPGAs for Starshield projects.
• Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
• Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
• Work closely with verification team to ensure all aspects of the design are covered and verified.
• Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
• Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

Benefits

• You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.
• You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks.
• You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year.
• Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Number of Employees: 5,001-10,000 employees