Principal Analog Mixed-Signal CAD Engineer

Astera Labs•San Jose, CA

About The Position

We are seeking a Principal CAD Engineer to architect, build, and maintain an integrated CAD infrastructure that enables seamless collaboration across analog/mixed-signal (AMS), digital RTL, physical design, and verification/validation teams. You will be the technical owner for cross-domain design environments ensuring reliability, scalability, and reproducibility across IP and SoC programs. This role combines EDA flow knowledge, and methodology knowledge. You will partner with design and verification leaders to define best practices, establish flows, and deliver a first-class designer experience from concept to tape-out.

Requirements

10+ years in CAD/EDA methodology development for IP/SoC programs across AMS and digital domains (advanced nodes preferred: 7 nm → 3 nm or equivalent).
Deep hands-on expertise with major EDA ecosystems (Cadence, Synopsys, Siemens).
Strong scripting/automation: Python, Perl, shell scripting, Cadence Skill, Tcl
HPC experience: LSF/SLURM, license servers monitoring/logging.
Version control and data management: Git/Perforce
Understanding of timing verification, SI, EM/IR, physical verification, library/PDK fundamentals, and foundry deliverables.

Nice To Haves

End-to-end flow integration across AMS, digital, PD, and verification disciplines.
Performance tuning: distributed resource management, memory/CPU/GPU utilization, and license efficiency.
Ability to abstract complex flows into modular components and standard interfaces.
Influence across organizations; mentor junior CAD engineers and power users.
Clear documentation, and effective training for current and new team members.