Power Methodology and Modeling Engineer - New College Grad 2026

NVIDIA•Austin, TX

About The Position

As a member of the Architecture Energy Modeling Team, you will collaborate with Architects, ASIC Design Engineers, Low Power Engineers, Performance Engineers, Software Engineers, and Physical Design teams to study and implement energy modeling techniques for NVIDIA's next generation GPUs, CPUs and Tegra SOCs. Your contributions will help us understand energy usage in graphics and AI workloads and make improvements in architecture, design, and power management. Today, NVIDIA is tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Come join the team and see how we can make a lasting impact on the world!

Requirements

Pursuing or recently completed a BS, MS or PhD in Electrical or Computer Engineering or equivalent experience.
Strong coding skills, preferably in Python, C++.
Ability to formulate and analyze algorithms, and comment on their runtime and memory complexities.
Understanding of VLSI, digital design, and computer architecture concepts.
Basic understanding of fundamental concepts of power and energy consumption, estimation, and low power design.
Basic understanding of chip design process from RTL design to tape-out.

Nice To Haves

Background in machine learning, AI, and/or statistical modeling is a plus.
Desire to bring quantitative decision-making and analytics to improve the energy efficiency of our products.

Responsibilities

Define and implement tools and methodologies for efficient data generation from post layout netlists to feed into data movement power analytical model.
Develop tools and infrastructure to sanitize each metric in the model to achieve high correlation accuracy.
Define and implement tools and methodologies for efficient integration of power models with performance tools.
Identify runtime and memory limitation of existing flows and tools to speedup model delivery process.
Mine data from pre- and post-silicon performance runs to find important data paths and bottlenecks.
Give feedback to design teams and improve power efficiency.
Work with floorplan, performance, verification and emulation methodology and infrastructure development teams to integrate data movement power models.
Experiment with various ML techniques to answer what-if design questions and set proper power/energy targets for next generation chips.
Enable efficient storage and retrieval of data from database.
Enable easy visualization of data using platforms such as PowerBI, OpenSearch.