Power Management Design Engineer

Qualcomm-posted 27 days ago
$140,000 - $210,000/Yr
Full-time • Mid Level
San Diego, CA
5,001-10,000 employees
Computer and Electronic Product Manufacturing
Resume
Match Score
Upload and Match ResumeTrack Jobs with Teal

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. Candidate will be responsible for design/developing next generation power control systems. Candidate will be working on ASIC based on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI development cycle like architecture, micro architecture, RTL design along with interactions with verification, Synthesis & PD teams for design convergence.

  • Digital design and development (RTL) working in close collaboration with Multi-site leads across US and India
  • Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC
  • Design and implement defined tasks independently.
  • Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.
  • Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc.
  • 5 to 8 years of strong experience in digital front end design for ASICs
  • Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains
  • Familiar with UPF and power domain crossing
  • Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI
  • Experience in low power design methodology and clock domain crossing designs
  • Experience in Spyglass Lint/CDC checks and waiver creation
  • Experience in formal verification with Cadence LEC
  • Understanding of full RTL to GDS flow to interact with DFT and PD teams
  • Expertise in Perl, TCL language
  • Good documentation skills
  • Should possess good communication skills to ensure effective interaction with Engineering Management and team members.
  • Should be self-motivated with good teamwork attitude and need to function with minimal guidance or supervision
  • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  • OR
  • Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  • OR
  • PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
  • Expertise in post-Si debug is a plus
Track Jobs with Teal

Job Search Resources

•
AI Resume Builder
•
Power Engineer Resume Examples
•
Cover Letter Examples

Tools

Career Hubs

Guides

Company

© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service