This is a full-time, on-site role for a Post Silicon Electrical Validation Engineer based in San Jose, CA, in the Cadence IP group. The engineer will be responsible for validating the electrical performance of our internal silicon test chips, debugging silicon issues by collaborating with the analog and digital design teams and releasing high quality characterization reports. The role involves collaborating with cross-functional teams to ensure the reliability and functionality of the product. Why Cadence? Cadence is at the forefront when it comes to the development of bleeding edge technology SERDES designs such as PCIe Gen7, 224Gbps Ethernet amongst other protocols and joining us gives you a golden opportunity to partner in our progress.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
Job Type
Full-time
Career Level
Entry Level
Industry
Ambulatory Health Care Services
Number of Employees
5,001-10,000 employees