Physical Design - STA

Tenstorrent

170d • $100,000 - $500,000

About The Position

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a Timing Engineer to join our silicon team. In this role, you’ll drive static timing analysis and closure for complex, high-performance designs. You’ll collaborate closely with logic, DFT, and physical design teams to debug constraints, optimize paths, and ensure our chips meet performance targets across corners and modes. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Requirements

• 7+ years of industry experience and a proven record of successful tapeouts.
• Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• Proficiency in writing and debugging SDC constraints, creating ECOs, and developing closure strategies.
• Strong scripting skills in Python, Perl, and TCL to support automation and flow development.
• Familiarity with SPICE modeling and worst-case corner analysis.

Nice To Haves

• Experience with advanced STA methodologies tailored to modern sub-micron process technologies.
• Ability to influence chip performance through timing methodology innovation and automation.

Responsibilities

• Drive static timing analysis and closure for complex, high-performance designs.
• Collaborate closely with logic, DFT, and physical design teams to debug constraints and optimize paths.
• Ensure chips meet performance targets across corners and modes.

Benefits

• Highly competitive compensation package including base and variable compensation targets.
• Equal opportunity employer.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 501-1,000 employees