Physical Design Lead – Custom Silicon Management

Apple-posted 4 months ago
Senior
Cupertino, CA
5,001-10,000 employees
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The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleTV. We have an extraordinary opportunity for senior level engineers to drive and lead technical engagements between Apple and silicon suppliers working on groundbreaking technologies. We are looking for a remarkable Physical Design Lead to work with a highly hardworking Custom Silicon team at Apple to design and develop innovative chips for the coolest products. This position focuses specifically on supporting Physical Design and related activities for the chips.

  • Audit vendor PD flows and methodologies for any holes and set up issues.
  • Suggest improvements to their methodology to optimize it to obtain the best QoR for Apple chips.
  • Work closely with the internal teams like systems and program management to ensure that the vendor PD implementation team is meeting the design goals.
  • Work closely with specialists from other teams like the packaging, process etc. to resolve any issues in the project which are in an area closely related to PD.
  • Conduct periodic design reviews - with deep technical dives - to make sure the project is tracking to the schedule and maintaining a high quality of work.
  • Review all the final PD, STA, SI, Electrical analysis reports and sign-off on them for tapeout approval.
  • Provide post tapeout support to work on ECOs and debug, if required.
  • Adhere to a strict and consistent standard of operation across all vendors and projects.
  • Maintain a professional relationship with the vendor and yet walk the fine line to maintain the customer-vendor distance.
  • BS degree.
  • Physical Design experience.
  • Knowledge of digital design concepts.
  • 10+ years of relevant industry experience.
  • Experience leading physical design teams.
  • Track record of having taped out a number of complex chips - from gates to GDS.
  • Working knowledge of front-end design methodology including basic RTL coding, synthesis methodology, timing constraints generation, multiple clock domain handling, low power techniques.
  • In depth practical, hands-on knowledge of the entire P&R methodology - including but not limited to - IO planning, ESD techniques, floor planning, power planning, clock tree synthesis, MCMM timing closure, routing, DFM techniques and physical verification.
  • Working knowledge of at least one of the industry CAD tools - Cadence, Synopsys, Mentor or Atoptech.
  • Proficient in Static Timing Analysis and the techniques used for timing closure and noise avoidance / fixing.
  • Hands-on experience in Power and Signal Integrity analysis.
  • Ability to debug and fix LVS, DRC, Antenna, ERC issues.
  • Familiarity with the best analog layout design practices for sensitive circuits like OpAmp, matching pair, etc.
  • Mixed signal SoC tapeouts involving multiple instances of analog IPs.
  • Low power / leakage management methodology and techniques.
  • Extraction and characterization of IP elements.
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