Join Altera, a pioneer in programmable logic solutions, where innovation meets practicality. We empower system, semiconductor, and technology companies to differentiate and excel in their markets rapidly and cost-effectively. Our legacy of innovation is matched by our commitment to our clients, whom we serve through a robust distribution network and a dedicated sales force. Our portfolio spans programmable logic products, acceleration platforms, software, and IP, all designed to accelerate the pace of innovation. As an Physical Design Intern , you will be responsible for helping implement Altera IPs such as PCIe, Ethernet, CXL and DR.. Key responsibilities on the PD team depending on project roles: Help in all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Utilizing scripting to run regressions & automate flows. Analyzing logs and reports to debug and recommend fixes. Interactions with local and remote teams. What We Want to See Pursuing a University Degree (e.g. EE, CE, CS or related fields) Digital design skills (FPGA or ASIC), using Verilog/VHDL/System Verilog and related design flows Scripting knowledge (e.g. Python, Tcl) Thirst for learning and a good self-starter Loves working as part of a team, with excellent communication skills. What We Value A mindset focused on engineering excellence and continuous improvement . Passion for automation and using AI to solve real-world problems. Initiative to observe, learn, and propose impactful solutions. Willingness to work in a lean and collaborative environment.