In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be a part of the chip implementation team developing flows and methodologies for workflow automation, data management, metric collection and dashboarding for physical design Electronic Design Automation (EDA) tools within the Google Compute Engine environment. You will survey industry trends, perform technical evaluations of vendors, provide recommendations and employ best practices. Your work will streamline ASIC physical design workflows, make our team of physical design engineers more efficient, and help ensure high quality of results for ASIC tapeouts. You will work with industry-standard physical design EDA tools and RTL To GDS CAD flows such as place and route, EM/IR, static timing, etc. You will also possess a good command of common scripting languages.