Physical Design Engineer

Waymo • Mountain View, CA

104d • $204,000 - $259,000

About The Position

Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo’s fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states. Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms.

Requirements

• 6+ years of experience on PD design tasks in advanced silicon nodes with a minimum of 3 tapeouts.
• Expertise in defining and developing the signoff methodology across multiple domains, including static timing analysis (STA), power integrity (EM/IR), and physical verification (DRC/LVS).
• Deep knowledge of STA and proficient in timing constraints with a demonstrated ability to generate, maintain, and verify SDC files.
• Experience with multi-power-domain sub-system and chip-top level assembly/closure.
• Familiar with UPF based PD flow and methodology.
• Ability to automate EDA tasks through scripting.
• Competency with TCL and Python.
• Excellent verbal and written communication skills and demonstrated capability to work under tight schedule.

Nice To Haves

• Experience with owning complex, high frequency blocks from RTL-to-GDS with an understanding of floorplanning, synthesis, place and route (including CTS), timing closure, and sign off.
• Experience with CAD flow development.
• Experience working with external partners on PD closure.
• Understanding of DFT including Scan, MBIST and LBIST.
• Deep understanding of performance, power and area (PPA) tradeoffs.
• Strong experience with back end flows (LEC, PI/SI, DRC/LVS, etc).

Responsibilities

• Participate in the Physical Design of advanced silicon for our self-driving cars.
• Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS.
• Collaborate with internal logic and internal and external PD teams to achieve the best PPA possible.
• Conduct feasibility studies for new microarchitectures.
• Optimize runs for finished RTL.

Benefits

• Discretionary annual bonus program
• Equity incentive plan
• Generous Company benefits program

What This Job Offers

• Job Type: Full-time
• Number of Employees: 1,001-5,000 employees