Physical Design Engineer

Bitdeer•San Jose, CA

48d

About The Position

Bitdeer Technologies Group (Nasdaq: BTDR) is a world-leading technology company for Bitcoin mining. Bitdeer is committed to providing comprehensive computing solutions for its customers. The Company handles complex processes involved in computing such as equipment procurement, transport logistics, datacenter design and construction, equipment management, and daily operations. The Company also offers advanced cloud capabilities to customers with high demand for artificial intelligence. Headquartered in Singapore, Bitdeer has deployed datacenters in the United States, Norway, and Bhutan. Bitdeer is seeking a highly skilled Physical Design Engineer with expertise in full-chip physical design. You will be instrumental in the complete physical implementation of high-performance and low-power digital circuits, taking the design from netlist to GDSII sign-off. This is a critical role that requires deep expertise in all aspects of the backend design flow and a commitment to achieving best-in-class power, performance, and area (PPA) targets on cutting-edge process nodes.

Requirements

PhD preferred in Electrical Engineering or Computer Engineering
Proficiency in advanced low-power techniques and experience with UPF/CPF implementation.
Proven track record in physical implementation on 7nm, 5nm, or smaller process technologies.
Strong debugging and root cause analysis skills for complex timing and physical verification issues.
Expertise in achieving high-frequency clock closure on complex, deeply pipelined designs.

Responsibilities

Executing the complete physical design flow for digital blocks, ranging from small modules to multi-million gate sub-systems.
Performing floorplanning, power planning, cell placement, and clock tree synthesis (CTS) to meet strict timing, power, and area constraints.
Driving and resolving complex issues in static timing analysis (STA), including setting up and signing off on all timing corners (e.g., PrimeTime).
Conducting extensive sign-off checks, including formal verification (LEC), design rule checking (DRC), layout vs. schematic (LVS), and electrical rule checking (ERC).
Implementing and optimizing sophisticated low-power techniques (e.g., multi-Vt, power gating, retention cells) across the design.
Using industry-standard electronic design automation (EDA) tools from vendors like Cadence (e.g., Innovus, Genus) or Synopsys (e.g., Fusion Compiler, IC Compiler II).
Developing, maintaining, and improving automated physical design flows and methodologies using scripting languages like TCL, Perl, or Python.
Collaborating closely with the front-end design, logic design, and CAD teams to ensure smooth handoffs and first-pass silicon success.

Benefits

A culture that values authenticity and diversity of thoughts and backgrounds;
An inclusive and respectable environment with open workspaces and exciting start-up spirit;
Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
Ability to contribute directly and make an impact on the future of the digital asset industry;
Involvement in new projects, developing processes/systems;
Personal accountability, autonomy, fast growth, and learning opportunities;
Attractive welfare benefits and developmental opportunities such as training and mentoring.

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