Physical Design Engineer (AS-64000922)

Cirrus Logic•Austin, TX

10h•Hybrid

About The Position

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldnât do it without our extraordinary workforce â and thatâs where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! Cirrus Logic is looking for an expert Physical Design Engineer to join its Implementation team. You will be part of a team working on implementing industry-leading mixed-signal SoC for consumer mobile audio markets. This role would suit a candidate with an ability to work independently and as part of a wider design team.

Requirements

Bachelor's or Master's in Electrical Engineering and 5+ years of industry experience in a Logic design or Physical Design position.
Strong solid understanding of RTL design, and the ideal candidate should be familiar with Cadence Genus/Innovus and Synopsys Design Compiler/ICC/Fusion Compiler
You should have Primetime, Conformal LEC, and ATPG.
You will also have a solid understanding of scan insertion, and ATPG.
Good communication and collaboration skills.

Nice To Haves

We will look to have you be involved in design/architecture reviews which will help add to the overall progress and improvement of the team.
We will be defining physical design methodologies and flow automation.
Ability to perform debug/analysis skills for designs, library, and technology files.
Ability to provide mentorship and guidance to junior engineers and be a very effective teammate.

Responsibilities

We will incorporate you on a team that is involved in all aspects of physical implementation from RTL to GDSII.
Perform RTL synthesis and scan stitching.
Apply deep knowledge of timing optimization and experience with ECO generation to analyze and fix timing issues in 40nm, 28nm and below.
You will be defining and debugging Timing Constraints and performing STA using industry-standard STA engines and a deep understanding of timing correlation to achieve timing closure.
Build timing constraints for the entire chip in a team environment.
Knowledge of automating and advancing flows using proficiency in Perl/Tcl scripting.
Analyze power constraints and chip floor plan.
You will analyze clock distribution on full-chip assembly.
Physical design-related flow development, tool evaluation, flow automation, QA and improvement.
You will develop Placement & Route structures for a complete ASIC design.
Build Static Timing Analysis, timing closure, ECO and tape-out.
IR Drop analysis and improvement on almost all designs