Physical Design Engineer

Quest Global

36d•$130,000 - $180,000•Onsite

About The Position

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries. We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we're eager to hear from you. The achievers and courageous challenge-crushers we seek, have the following characteristics and skills

Requirements

MSEE/MSCS 10+ years (BSEE/BSCS 12+ years)
Expertise in Cadence Innovus/Atop physical design tools
Experience on Calibre LVS/DRC
Low power, signal integrity experience
Work closely with RTL & DFT designers
Strong TCL/Python scripting knowledge required, Perl is a plus.
Good debug skill and be able to work around issues
Tape out experience must be a good team player

Responsibilities

Perform physical design of 2nm/3nm/5nm mutli-GHz IP for network switch products.
Be able to come up with floorplan, powerplan, cts and routing of the design using state-of-art EDA tools like Innovus.
Work closely with designers and must be able to write TCL script to perform custom/semi-custom standard cells placements/clock tree adjustments/routing to achieve design specs (STA/IR/EM/LVS/DRC).
Good timing analysis and CTS knowledge is required.