Physical Design Engineer - New College Grad 2026

NVIDIAUs, CA
14h$96,000 - $184,000

About The Position

We are now looking for a Physical Design Engineer! NVIDIA has continuously pioneered and reinvented itself over two decades through various avenues of computing: Graphics, High Performance Computing, Artificial Intelligence, Research, and more. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can solve, and that matter to the world. This is our life’s work, to amplify human creativity, intelligence, and technology. Today, visual computing is becoming increasingly central to how people interact with technology, and there has never been a more exciting time to join our team. We are looking for a Physical Design Engineer who will be responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets, and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets.

Requirements

  • Completing an BSEE, MSEE or PhD (or equivalent experience).
  • Deep understanding of VLSI and Physical Design related basics & concepts.
  • Possess a deep understanding of static timing analysis, clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis.
  • Experience in scripting and programming using several of the following languages/tools: Perl, C, C++, TCL, Scheme, Skill, or Make.
  • Previous internship or project experience in physical design implementation

Responsibilities

  • As a member of the team, you will participate in the efforts in establishing CAD and physical design methodologies (flow and tools development) as well as implementation.
  • Your day to day will include developing chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects.
  • This position requires you to work with EDA vendor (Synopsys, Cadence, Mentor, etc.) tool suites such as: ICC2,PrimeTime, dc_shell, Innovus, SeaHawk.
  • You will interact with a diverse team engineers.

Benefits

  • You will also be eligible for equity and benefits

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What This Job Offers

Job Type

Full-time

Career Level

Entry Level

Number of Employees

5,001-10,000 employees

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