Physical Design Engineer Intern - Bachelor's Degree
About The Position
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell CCDS (Central CAD and Design Services) PD engineers are working on cutting edge SoC (System on a Chip), ASIC, High Performance Processor, Digital/Analog and Mix-signal Circuit IP design for our clients inside and outside of Marvell with the best performance, power, and area. By employing the industry leading EDA tools, methodology, and advanced technologies, the intern will involve on-the-job training and mentorship on an active design. The training will cover at least one aspect of PD activities (e.g. Automated Place & Route, Static Timing Analysis, Physical Verification, etc.). What You Can Expect One or more of the following: Block lever floorplan, place and route, timing analysis/closure, ECO implementation. Power grid or custom route. Physical verifications and DRC/LVS clean-up.
Requirements
- Candidate must be enrolled in a BS program in Electrical Engineering, Computer Engineering, Computer Science, with a graduation date in fall of 2026 or spring 2027.
- Knowledge of digital logic, circuit design, and/or computer architecture.
- Exposure to scripting languages such as Perl/Python and/or tcl.
- Detail oriented, self-motivated team worker, good verbal and written communication skills.
Nice To Haves
- Previous experience on physical design and automatic place and route a plus. i.e. Knowledge of Synopsys/Magma/Cadence place and route tools.
- Previous experience on synthesis/STA a plus.
Responsibilities
- Block lever floorplan, place and route, timing analysis/closure, ECO implementation.
- Power grid or custom route.
- Physical verifications and DRC/LVS clean-up.
Benefits
- medical, dental and vision coverage
- perks and discount programs
- wellness & mental health support including coaching and therapy
- paid holidays
- paid volunteer days
- paid sick time
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What This Job Offers
Career Level
Intern
Industry
Computer and Electronic Product Manufacturing
Number of Employees
5,001-10,000 employees
