PHY RTL Design Engineer

Apple • San Diego, CA

9d

About The Position

Come join Apple’s growing wireless silicon development team. Our wireless SOC
organization is responsible for all aspects of wireless silicon development.
With a particular emphasis on highly energy-efficient design and new
technologies that transform the user experience at the product level, all of
which is driven by a world-class vertically integrated engineering team spanning
RF/Analog architecture, and design, Systems/PHY/MAC architecture and design,
VLSI/RTL design and integration, Emulation, Design Verification, Test and
Validation, and FW/SW engineering.

DESCRIPTION

Develop signal processing intensive design for wireless communication SoCs,
including: Writing specifications, other documents, and defining
Microarchitecture based on MATLAB/C system model. Architecting area and power.
Efficient low latency designs with scalabilities and flexibilities. Work with
algorithm and software team to ensure performance and power efficiency. Power
and Area efficient RTL logic design, and DV support. Running tools to ensure
lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in
design of signal processing Wireless protocols.

Requirements

• Bachelors degree in related field
• Understanding of DSP fundamentals
• Digital Communications knowledge
• Proficiency in RTL Design

Nice To Haves

• Strong fixed-point knowledge
• Understanding of Decoders - Viterbi, LDPC, Polar
• Understanding of Filter design, multi-radix implementation, and compromises
• Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis
• Background in computer architecture
• Ability to work well in a team and be productive under ambitious schedules
• Should exhibit excellent interpersonal skills and be self-motivated and well-organized
• Understanding of FPGA and/or emulation platform desired
• Excellent communication skills – both written, and oral

Responsibilities

• Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model
• Architecting area and power
• Efficient low latency designs with scalabilities and flexibilities
• Work with algorithm and software team to ensure performance and power efficiency
• Power and Area efficient RTL logic design, and DV support
• Running tools to ensure lint and CDC/RDC clean design
• Synthesis and timing constraints
• Experience in design of signal processing Wireless protocols

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level