PHY RTL Design Engineer

Apple • San Diego, CA

83d

About The Position

Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.

Requirements

• Bachelor's degree and 3+ years of relevant industry experience.
• Understanding of DSP fundamentals.
• Knowledge of Digital Communications.
• Proficiency in RTL Design.

Nice To Haves

• Familiarity with UVM DV environment and AI based efficiency improvement flows.
• Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications.
• Understanding of Decoders - Viterbi, LDPC, Polar.
• Understanding of Filter design, multi-radix implementation, and compromises.
• Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis.
• Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation.
• Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP.
• Background in computer architecture.
• Experience with Bus fabric, especially APB/AHB/AXI.
• Knowledge of power management with multiple power domains.
• Ability to work well in a team and be productive under ambitious schedules.
• Excellent interpersonal skills and self-motivated and well-organized.
• Experience with FPGA and/or emulation platform.
• Excellent communication skills – both written and oral.

Responsibilities

• Develop signal processing intensive design for wireless communication SoCs.
• Write specifications and other documents, and define Microarchitecture based on MATLAB/C system model.
• Architect area and power for efficient low latency designs with scalability and flexibility.
• Work with algorithm and software team to ensure performance and power efficiency.
• Perform power and area efficient RTL logic design, and provide DV support.
• Run tools to ensure lint and CDC/RDC clean design.
• Manage synthesis and timing constraints.
• Design signal processing Wireless protocols.

What This Job Offers

• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees