Performance Architect

Cadence Design Systems•Austin, TX

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Performance Architect Location Austin, TX Role Overview We are seeking a Performance Architect to drive system‑level performance architecture for ARM‑based SoCs and chiplet platforms. In this role, you will define, analyze, and optimize performance across CPUs, interconnect, memory subsystems, and accelerators, working closely with system architects, IP teams, design, and software. This is a senior technical role requiring deep expertise in ARM architectures, memory systems, and end‑to‑end performance modeling, with the ability to influence architecture decisions early and guide teams through implementation and validation.

Requirements

10+ years of experience in SoC, system, or performance architecture (staff‑level expectations).
Proven experience working on ARM‑based systems in data center, automotive, mobile, or embedded domains.
Deep understanding of computer architecture: Memory hierarchy and bandwidth/latency trade‑offs
Strong knowledge of ARM architecture and ecosystem: ARMv8/ARMv9 CPUs Performance monitoring (PMU/AMU) System memory management concepts (SMMU, TLBs, page tables)
Solid understanding of interconnects and fabrics (NoC, coherency protocols, QoS).
Experience with performance modeling and analysis techniques

Responsibilities

System & SoC Performance Architecture Define performance requirements, KPIs, and budgets across CPU, interconnect, memory, and I/O subsystems.
Drive architectural trade‑offs involving latency, bandwidth, throughput, power, and area.
Evaluate and optimize performance for heterogeneous workloads (NPU/AI, ISP, VISION, I/O).
Interconnect & Chiplet Performance Evaluate and optimize NoC / fabric architectures (latency, bandwidth, congestion, QoS).
Analyze performance impacts of chiplet partitioning, die‑to‑die interconnects (e.g., UCIe‑class links), and protocol overheads.
Identify bottlenecks across chiplet boundaries and propose architectural mitigations.
Performance Modeling & Analysis Build and maintain system‑level performance models (transaction‑level, analytical, or cycle‑approximate).
Perform workload‑driven studies using synthetic traffic, benchmarks, and real software traces.
Correlate model results with RTL, emulation, or silicon data as designs mature.
Clearly communicate performance findings and recommendations to cross‑functional teams.
Cross‑Functional Leadership Work closely with system architects, IP architects, design, verification, and software teams.
Provide technical leadership and mentorship on performance topics.
Influence architectural decisions through data‑driven analysis and clear technical communication.