Packaging Engineering Intern - MS/PhD - Santa Clara
About The Position
Change the world. Love your job. Interface across various work areas and organizations to help with the design, development, and analysis of different semiconductor packaging technologies to enable differentiation for TI's analog and embedded processing products. Assignments may include participation in cross-functional teams to develop internal and external solutions for semiconductor packaging technologies, including Wirebond, Flip Chip, Modules, SIPs and other advanced packages at different stages of readiness. Cultivate packaging advancements with work in material, mechanical, thermal, and electrical characterization. TI's innovative packaging technologies are designed to solve customers' problems by delivering advances in miniaturization, integration, high reliability, high performance, and low power. Put your talent to work with us as a Packaging Engineering Intern !
Requirements
- Currently pursuing an Masters degree in Mechanical Engineering, Materials Science, Chemical Engineering, Physics or Electrical Engineering.
- Cumulative 3.0/4.0 GPA or higher
Nice To Haves
- Semiconductor packaging knowledge is preferred (processes, assembly, reliability, materials, characterization, FA)
- Demonstrated analytical and problem solving skills
- Strong written and verbal communication skills
- Ability to work in teams and collaborate effectively with people in different functions
- Strong time management skills that enable on-time project delivery
- Ability to build strong, influential relationships
- Ability to work effectively in a fast-paced and rapidly changing environment
- Ability to take the initiative and drive for results
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What This Job Offers
Career Level
Intern
Number of Employees
5,001-10,000 employees
