Package Developer

Solidigm•Rancho Cordova, CA

6d•Onsite

About The Position

Solidigm is seeking an innovative Package Developer to support pathfinding and development of package technologies for Solid State Drive (SSD) and NAND flash storage card applications. In this position, you will be responsible for innovation in packaging technologies to meet the SSD product roadmap. In addition, you will be responsible for the development of package design, including package stack-up and configuration, substrate design, design collaterals, package pin assignments, signal integrity simulation and assessment, package data sheets, and interface with internal/external standards forums. Other responsibilities include driving/tracking package design milestones, integrating product requirements into packaging solutions, identifying and resolving packaging design issues, and communicating design status. Perform die fit analysis, stack-up, reference plane, and power distribution for multi-die NAND packages. Define device package pin-out and I/O bus interface. Integrate design requirements from high-speed electrical signaling, high-volume assembly design rules, package and/or PCB design rules, automated test, and emerging IC packaging techniques. Perform package and/or PCB routing study analysis for tradeoffs in cost and performance. Perform design, analysis, and validation of off-silicon platform interconnects, with a focus on memory interfaces such as DDR2 or on high-speed differential I/O interfaces such as SATA or PCIe. Define and develop electrical modeling capabilities and analysis techniques for busses and interconnects. Work with subcontractors in advancing packaging design rules for product roadmap intercept.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, Material Science, or a related technical field.
Minimum of 5 years of experience in package architecture, IC packaging, or PCB design engineering.
Expertise with advanced packaging technologies, signal integrity simulation, and electrical analysis of high-speed interconnects (e.g., DDR2, SATA, PCIe, etc.).
Proven track record of successfully developing package design processes, including stack-up configuration, substrate design, die-fit analysis, and pin-out definition.
Hands-on experience with signal integrity simulation tools such as HFSS, Sigrity, or CST Microwave Studio.
Familiarity with packaging technology considerations such as die fit analysis, power distribution planning, routing tradeoff studies, and signal integrity concerns.
Strong project management and communication skills to manage cross-functional teams across both internal teams and subcontractors.
Ability to represent Solidigm in industry standard forums, collaborate effectively across multiple divisions, and integrate standards into product development.

Nice To Haves

Master's degree or PhD in Electrical Engineering, Mechanical Engineering, or Material Science.
Over 8 years of in-depth technical expertise in IC packaging design or NAND product development.
Knowledge of emerging packaging technologies and techniques (e.g., wafer-level packaging, 2.5D/3D IC integration).
Familiarity with JEDEC, ONFI, and other industry standards for memory and SSD packaging.
Advanced proficiency in package modeling tools and techniques.
Solid understanding of solder joint reliability failure modes and the factors influencing reliability (design, material quality, soldering techniques).
Solid understanding of package substrate design practices from a signal integrity and power integrity perspective.
Knowledge of electrical analysis and design of high-speed buses (differential and single ended) as well as familiarity with simulation, modeling, and analysis tools.
Understanding of thermal analysis and optimization related to multi-die NAND packages.
Experience driving packaging technology innovation by partnering with subcontractors and suppliers.
Ability to coordinate across multiple business divisions and contribute to the roadmap of SSD/NAND packaging technologies.

Responsibilities

Innovation in packaging technologies to meet the SSD product roadmap.
Development of package design, including package stack-up and configuration, substrate design, design collaterals, package pin assignments, signal integrity simulation and assessment, package data sheets, and interface with internal/external standards forums.
Driving/tracking package design milestones
Integrating product requirements into packaging solutions
Identifying and resolving packaging design issues
Communicating design status
Perform die fit analysis, stack-up, reference plane, and power distribution for multi-die NAND packages.
Define device package pin-out and I/O bus interface.
Integrate design requirements from high-speed electrical signaling, high-volume assembly design rules, package and/or PCB design rules, automated test, and emerging IC packaging techniques.
Perform package and/or PCB routing study analysis for tradeoffs in cost and performance.
Perform design, analysis, and validation of off-silicon platform interconnects, with a focus on memory interfaces such as DDR2 or on high-speed differential I/O interfaces such as SATA or PCIe.
Define and develop electrical modeling capabilities and analysis techniques for busses and interconnects.
Work with subcontractors in advancing packaging design rules for product roadmap intercept.