Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer

Qualcomm • San Diego, CA

83d • $140,000 - $210,000

About The Position

Next Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team is looking for ASIC Design Engineers for the next generation high speed LPDDR/DDR memory subsystems. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products. The candidate will work on architecture, design (RTL coding), and deployment of the next generation, high-speed memory subsystems into QCT products. You will develop or contribute to the development of design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.

Requirements

• Bachelor's or Master's degree in Science, Engineering, or related field.
• 5+ years of ASIC design, RTL coding, front-end digital design experience.
• Experience with LPDDR memory and cache controller, NoC based architectures.
• Experience with on-chip tightly coupled SRAM & L3 cache controller architecture/design.
• Experience with x86 or ARM CPU/bus architectures.
• Knowledge of ordering of memory transactions and methods to enforce proper ordering.

Nice To Haves

• 5-10 years of ASIC design (RTL coding).
• Exposure to RTL Design Verification flows.
• Bachelor's degree in Electrical or Computer Engineering.
• Master's degree preferred.

Responsibilities

• Work on architecture, design (RTL coding), and deployment of high-speed memory subsystems.
• Develop or contribute to the development of design specifications.
• Drive the micro-architecture of portions of the logic design.
• Implement and deliver RTL.
• Collaborate with verification engineers to deliver high quality designs.
• Debug designs and provide support when integrated into the rest of the chip.
• Perform synthesis, timing closure, physical design support, gate level simulations, and power analysis.
• Contribute to the improvement in design methodology to enhance productivity and quality.

Benefits

• $140,000.00 - $210,000.00 salary range.
• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants.
• Comprehensive benefits package designed to support success at work, home, and play.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Bachelor's degree