About The Position

Perform semiconductor design engineering assignments, including chip‑level circuit design, layout collaboration, circuit checking, and documentation. Assist with gate‑level to full‑chip build, layout, and improvement of memory circuit efficiency. Complete circuit simulations using industry‑standard tools such as SPICE and Verilog; analyze and debug results. Design and develop schematic blocks including memory arrays, control logic, address decode, datapath, and internal test logic. Evaluate design architecture tradeoffs and understand their impact on power, performance, die size, and reliability. Import and analyze layout parasitic information within circuit simulation environments. Interpret device specifications and translate them into die‑level circuit functionality across operating ranges. Support test chip definition, silicon validation strategies, and lab correlation efforts. Collaborate with Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to ensure manufacturability. Find opportunities to drive competitive advantage through innovative design concepts.

Requirements

  • Bachelor's degree in Electrical Engineering or higher
  • Basic understanding of memory applications and CMOS fundamentals
  • Solid base in circuit simulation setup, analysis, and debug
  • Strong written and verbal communication skills with the ability to convey complex technical concepts to peers and management

Nice To Haves

  • Experience with memory circuit design and performance optimization
  • Familiarity with CMOS process reliability limits
  • Exposure to silicon validation or test chip bring‑up activities
  • Demonstrated motivation to grow technical breadth and depth within collaborative, global teams

Responsibilities

  • chip‑level circuit design
  • layout collaboration
  • circuit checking
  • documentation
  • gate‑level to full‑chip build
  • layout
  • improvement of memory circuit efficiency
  • circuit simulations using industry‑standard tools such as SPICE and Verilog
  • analyze and debug results
  • Design and develop schematic blocks including memory arrays, control logic, address decode, datapath, and internal test logic
  • Evaluate design architecture tradeoffs and understand their impact on power, performance, die size, and reliability
  • Import and analyze layout parasitic information within circuit simulation environments
  • Interpret device specifications and translate them into die‑level circuit functionality across operating ranges
  • Support test chip definition, silicon validation strategies, and lab correlation efforts
  • Collaborate with Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to ensure manufacturability
  • Find opportunities to drive competitive advantage through innovative design concepts
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