Network Development Engineer, ML Infrastructure (High-Speed Interconnects)

xAI • Palo Alto, CA

5h • Onsite

About The Position

xAI is building at a furious pace with the latest compute and switching hardware to help people understand the universe. We are looking for exceptional ML Infrastructure Engineers with deep expertise in high-speed interconnect technologies to design, build, and optimize the network fabric that powers large-scale AI training and inference clusters. This strategic role will drive innovation in high-bandwidth, low-latency, power-efficient interconnects critical for AI/ML clusters based on advanced computing platforms.
You will have the opportunity to work on all modalities of interconnects connecting GPUs and switches both inside and between data centers, including our primary front and backend networks that train Grok and that customers use for inference. Engineers will own all aspects from design and development to build and operations. You will be expected to define and improve team processes and to contribute to scaling and maintenance efforts.
You will focus on the physical layer and system-level integration of copper (ACC, AEC, CPC) and optical (FRO, LRO/TRO, LPO, AOC, CPO) interconnects that directly determine the performance, power efficiency, scale, and cost of next-generation AI/ML clusters. This is a highly technical, hands-on role bridging ML cluster requirements with cutting-edge interconnect hardware — ideal for engineers who love both large-scale AI systems and the physics/engineering of 200G+ SerDes, PAM4, photonics, signal integrity and diagnostics.

Requirements

• At least 8+ years of hands-on experience in designing, deploying and operating high-speed copper and optical interconnects, preferably in a module design role or in a hyperscale datacenter environment.
• Master's or PhD degree in Electrical Engineering, Photonics or Physics.
• Deep knowledge of PAM4 SerDes performance, equalization, jitter, crosstalk.
• Solid operational understanding of FEC, Retimers, TIAs and Drivers.
• Deep knowledge of optical link budget analysis and performance metrics including TDECQ, OMA, Tcode, stressed receiver sensitivity and associated diagnostics.
• Expertise in transceiver components including CW lasers, SiPh PICs, EML, DSP, passive subassemblies, their failure modes and characterization.
• Knowledge of thermal, mechanical, power, signal integrity constraints in dense hardware.
• Knowledge of SiPh design process, yield improvement and reliability testing.
• Familiarity with CPO technologies and challenges/risk areas.
• Familiarity with subcomponent supply chains and global manufacturers, ODMs and CMs.
• Strong problem-solving skills and ability to thrive in a fast-paced, ambiguous setting.

Nice To Haves

• Experience designing hyper scale network infrastructure or large-scale GPU clusters and automating their entire deployment process.
• Proven track record in leading on-call rotations, incident response, and team development in high-stakes environments.
• A working understanding of RoCEv2.

Responsibilities

• Design, validate, and productize high-speed copper and optical connectivity solutions for AI clusters (100k+ GPU scale).
• Own vendor due diligence and onboarding for new 1.6T products including AEC and pluggable optical transceivers (DR4/8, FR4) including rigorous bring-up & characterization.
• Investigate the opportunity for LPO and LRO in our network.
• Evaluate early co-packaged and near-packaged engines for switches and GPUs.
• Pathfinding for new interconnect modalities including VCSEL, microLED, THz radio-based solutions to improve network economics and reliability.
• Work closely with vendors (transceiver, cable, SerDes, DSP, silicon photonics foundries) to influence roadmaps and ensure timely delivery of next-gen solutions.
• Collaborate with ML training teams to translate workload communication patterns into concrete interconnect topology and optical reconfigurability requirements.
• Perform system-level simulation of end-to-end fabric performance.
• Drive failure analysis, root cause, and corrective actions for interconnect-related issues in production clusters through fleet-level metrics gathering and analysis.
• Contribute to internal tooling and automation for interconnect health monitoring, telemetry, diagnostics, remediation and automated qualification pipelines.
• Stay current with industry standards (OIF CMIS, IEEE) and emerging technologies (multi-core/hollow-core fiber, 448G SerDes, TFLN, ring resonators)

Benefits

• Base salary is just one part of our total rewards package at X, which also includes equity, comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, and various other discounts and perks.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level