NAND Memory Package R&D Engineer

SolidigmRancho Cordova, CA
15h$121,280 - $194,100

About The Position

Solidigm is seeking an innovative NAND Memory Package Integration Engineer to support the pathfinding and development of package technologies for Solid State Drive (SSD). In this role, you’ll be responsible for pioneering packaging technologies to align with the SSD product roadmap. You’ll work with the wafer fab and Assembly Test Subcon in process integration & development. Other responsibilities include driving and tracking package design milestones, integrating product requirements into packaging solutions, identifying and resolving packaging design issues, and communicating design status.

Requirements

  • BS Physics, Chemistry, Chemical, Mechanical, Electrical, Material Science or other Engineering discipline
  • 5-10 years of experience in semiconductor package development
  • Knowledge in Silicon thin film processing and understanding of the interactions between silicon and Microelectronics package manufacturing
  • Familiar with Silicon layout design
  • Proficient in failure analysis at both silicon and package levels (EFA, PFA), design of experiments, and data analysis
  • Proven abilities in program management, communication, teamwork, planning, and prioritization

Nice To Haves

  • Solid understanding of package substrate design from a signal integrity perspective
  • Proficient with HSPICE, Ansoft Q2D/Q3D, or other field solvers
  • Skilled in high-speed signal integrity, power delivery, and DDR package design
  • Familiar with PCB assembly and package-to-board interconnects
  • Knowledgeable about flip chip packaging
  • Experience with AutoCAD and Cadence (APD, Editor, SIP)

Responsibilities

  • pioneering packaging technologies to align with the SSD product roadmap
  • working with the wafer fab and Assembly Test Subcon in process integration & development
  • driving and tracking package design milestones
  • integrating product requirements into packaging solutions
  • identifying and resolving packaging design issues
  • communicating design status
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