Mixed signal verification Engineer (Graduate)

Retym-posted about 2 months ago
Full-time • Entry Level
Austin, TX
11-50 employees
Professional, Scientific, and Technical Services
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We are seeking an engineer to join the Retym mixed-signal verification team. The role involves verifying digital and analog designs using behavioral modeling, SystemVerilog, UVM, and Cadence Virtuoso. You will contribute to developing cutting-edge technology for the next generation of high-speed communication systems.

  • Bachelor's degree (or higher) in Electrical Engineering
  • Experience 1-3 years
  • Exposure to digital design and verification using Verilog or SystemVerilog (through coursework, projects, or internships)
  • Basic understanding of digital, analog and mixed-signal circuit concepts
  • Familiarity with schematic design tools such as Cadence Virtuoso (academic)
  • Collaborative Environment: Ability to work in a team and learn from senior engineers while contributing to verification of analog/mixed-signal designs.
  • Communication: Clear written and verbal communication skills for documenting work, writing test plans, and presenting results. Demonstrated ability to ask questions, seek guidance, and share findings with multi-disciplinary teams.
  • Self leaner, highly motivated.
  • Familiarity with UVM (Universal Verification Methodology) concepts
  • Exposure to both Synopsys and Cadence tool flows through university or internship projects
  • Understanding of mixed-signal verification concepts, even if no direct industry experience
  • Relevant universtiy courses: o Advanced Design of Analog Circuits in Digital Processes o Digital System Design and/or Digital logic systems o Analog Electronics and/or Analog Integrated Circuits
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