Memory System Designer and Place and Route Engineer

Broadcom-posted 3 months ago

$108,000 - $172,800/Yr

Mid Level

5,001-10,000 employees

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We are looking for an energetic and passionate design engineer to join our Central Engineering Group and be part of a memory subsystem design team responsible for the development of large memory blocks and subsystems. Typically requires a minimum of 8 years of relevant experience and a Bachelor in Electrical Engineering.

Architect and design memory subsystems
Implement RTL of subsystem designs
Place and route (physical design)
Design closure: timing, DRC, LVS, EM/IR, etc.

Strong design skills
Ability to write and debug Verilog RTL code
Place and route expertise
Proficient in running STA, DRC, EM/IR tools, and attaining design closure
Ability to code in Python
Good understanding of synthesis tools and running synthesis
Capable of running and debugging logical equivalency checkers
Familiar with memory behavior
Proficient in writing automation scripts, and tools savvy
Good communication, interpersonal, and leadership skills
Motivated, self-driven, and good at multitasking

Medical, dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave and vacation time

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