Memory Subsystem Performance Architect

Qualcomm • San Diego, CA

1d

About The Position

We are looking for an experienced Memory Subsystem Performance Architect to lead HBM performance modeling, analysis, and optimization of high‑bandwidth memory subsystems for next‑generation SoCs. This role drives architecture exploration from early concept through post‑silicon, partnering closely with architecture, design, and software teams.

Requirements

• 3+ years of experience in performance modeling, memory architecture, or system architecture.
• Strong C++ proficiency; experience with SystemC/TLM modeling.
• Solid understanding of memory hierarchies and DRAM systems.

Nice To Haves

• Hands-on experience with HBM2/HBM2E/HBM3 architectures.
• Experience with AI/ML, GPU, or HPC-class SoCs.
• Familiarity with post‑silicon performance analysis and silicon correlation.
• Ability to translate performance data into clear architectural recommendations.

Responsibilities

• Develop and maintain C++ / SystemC performance models for HBM-based memory subsystems.
• Define and execute experiments to evaluate HBM architecture features, memory controller behavior, and system‑level trade-offs.
• Identify performance bottlenecks across HBM, interconnect, caches, and compute, and propose architecture improvements.
• Collaborate with cross‑functional teams (SoC, NoC, memory controller, power, software) to influence design decisions.
• Research and track industry trends and innovations in HBM, 3D-stacked memory, and advanced packaging.
• Support post‑silicon performance characterization, correlation, and model refinement.

Benefits

• competitive annual discretionary bonus program
• opportunity for annual RSU grants
• highly competitive benefits package is designed to support your success at work, at home, and at play

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 5,001-10,000 employees