Memory Subsystem Design Verification Engineer

Advanced Micro Devices, Inc•Austin, TX

2d•Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Memory Subsystem team is hiring Verification Engineers to contribute to the definition, design, and development of high-speed LPDDR/DDR memory subsystem solutions and associated IP. This role includes verification across multiple product lines and pre-silicon production-level firmware co-verification using hybrid co-simulation environments and Universal Verification Methodology (UVM). THE PERSON: In this role, you will design and implement advanced verification environments for memory subsystems and associated IP using System Verilog and UVM methodologies. You will develop and maintain test benches, co-verification frameworks, and test suites aligned with evolving firmware features, ensuring comprehensive coverage and robust verification from IP and subsystem levels through production. Responsibilities include integrating and debugging Memory VIP, analyzing coverage metrics, managing regressions, and collaborating with cross-functional teams to deliver end-to-end verification solutions. You will also adapt to new tools and frameworks, contribute improvements, and document results to support efficient and scalable verification processes.

Requirements

Proficiency in C/C++, System Verilog, UVM (object-oriented design), and scripting languages (e.g., Python, shell)
Experience in IP and subsystem verification with System Verilog/UVM and VCS
Background in testbench architecture, microarchitecture, and co-verification with firmware
Knowledge of code and functional coverage and how test plans map to cover goals
Ability to design and debug co-verification environments for production-level firmware
Experience developing transactor-based stimulus and maintaining test suites as features evolve
Ability to learn new toolsets/frameworks and contribute updates

Nice To Haves

Experience building monitors/checkers and developing SVA/OVL and synthesizable assertions
Verification experience with DDR/JEDEC standard IP, DDR PHY, or Memory Controllers
Experience verifying subsystems/components and applying methodologies to achieve subsystem verification
Familiarity with architectural models and SystemC
Experience with Zebu emulation for verification and debug
Firmware/hardware co-verification using UVM System Verilog, C-DPI, and gasket‑structured testbenches
Memory VIP integration, bring-up, and debug
End-to-end verification experience from front-end through lab bring-up.
Understanding of synchronization techniques (e.g., handshakes, message passing) and hardware-level clocking, including multi-domain simulation synchronization
Experience with Git and Perforce
Managing regressions and coverage databases
SoC IP knowledge and a high-level understanding of the role and interfaces of each IP

Responsibilities

design and implement advanced verification environments for memory subsystems and associated IP using System Verilog and UVM methodologies
develop and maintain test benches, co-verification frameworks, and test suites aligned with evolving firmware features, ensuring comprehensive coverage and robust verification from IP and subsystem levels through production
integrating and debugging Memory VIP
analyzing coverage metrics
managing regressions
collaborating with cross-functional teams to deliver end-to-end verification solutions
adapt to new tools and frameworks, contribute improvements, and document results to support efficient and scalable verification processes