Memory PHY Validation Engineer

Advanced Micro Devices, Inc•Austin, TX

13d

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the IO and Circuit Technologies Group, you will contribute to the development and productization of advanced high‑speed memory interface IP. In this position, you will join the High‑Speed IO Interface IP engineering team and work closely with architecture, IP design, physical design, SoC, platform, product, and other cross‑functional engineering teams. You will help deliver industry‑leading HBM, DDR, and LPDDR memory interface solutions from design through silicon implementation. THE PERSON: The ideal candidate brings strong technical capabilities, attention to detail, and clear communication skills. They collaborate effectively with silicon design engineers and multidisciplinary teams and demonstrate solid analytical and problem‑solving abilities when working on both pre‑silicon and post‑silicon challenges.

Nice To Haves

High-speed I/O design experience, including understanding of Tx (transceiver), Rx (Receiver), PLL (phase lock loop)/DLL, Clocking, Equalization techniques and circuits, Training algorithms and Firmware
Python and/or Perl programming for test scripts, data analysis, FW code creation/debug, should be familiar with UNIX and Windows environment
Ability to adapt learn new toolsets and frameworks
Basic understanding of Verilog RTL, digital circuits, as well as a general knowledge and experience of the backend physical flow
Laboratory experience, including hands-on use of equipment: Oscilloscopes, Signal generators, BERT, Logic analyzers, etc.

Responsibilities

Provide systems engineering and post-silicon support for HBM/DDR/LPDDR Memory interface IP
New products bring-up support from first silicon in the lab through initial production
Triage observations from silicon validation, and help debug issues with ATE, Platform, Firmware, and Characterization / Compliance teams
Provide expertise and support in silicon design, process, and integration flows for Memory Interface IP
Pre-Silicon engagement with internal and external PHY design teams, Platform, ATE, IP design, and Firmware teams
Perform and review analog circuit and mixed-signal design/analysis for high-speed I/O and Memory Interface IP in advanced process technologies