Memory PHY RTL Design Engineer

AMD • Santa Clara, CA

272d

About The Position

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

Requirements

• Digital design engineering experience
• Experienced with Verilog, System Verilog, C, and C++
• Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus
• Knowledge of clocking architectures, synchronization, and CDC methodology
• Experience with synthesis, Timing closure
• SERDES, DDR, Memory Controller, or MAC Design experience is preferred
• Proficient in debugging firmware and RTL code using simulation tools
• Strong understanding of computer organization/architecture
• Mixed signal RTL, Low power design experience is a plus
• Exposure to leadership or mentorship is an asset

Responsibilities

• RTL design for memory I/O PHY
• Digital Architecture development from pathfinding, coding, verification to physical implementation
• PHY link layer design, implementation & verification with Analog and System architect
• PHY Analog/Digital co-design
• Digital design and RTL coding
• Timing Synthesis & Drive Physical implementation
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the unit tests
• Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues

What This Job Offers

• Industry: Computer and Electronic Product Manufacturing
• Education Level: Bachelor's degree