Memory Chip Design Engineer

Western Digital • San Jose, CA

1d

About The Position

The job opening is for a full-time Research Staff Member in the Design Group in Western Digital's research department. The role will be a part of a multi-functional team whose aim is to develop and eventually commercialize Western Digital's strategic radiation hardened memory technology.

Requirements

• Minimum of a Bachelor's degree in Electrical Engineering, Physics, or closely related field with 8+ years of professional experience or a Ph.D. with 3+ years is required.
• Previous design layout, tape out and validation of high density memory chip designs
• Capability to develop design layout schedules that meet chip functional requirements and timelines
• Proficiency in Cadence Virtuoso (VXL), Mentor Graphics Calibre, or Synopsys IC Validator
• Capability to work closely with circuit designers to iterate on schematics and with process engineers to understand fabrication constraints
• Deep understanding of CMOS fabrication processes, Phase-Shift Mask Development and Multi-Patterning Techniques

Nice To Haves

• Experience developing memory cell models for inclusion in simulation tool environment, such as Verilog-A
• Experience with emerging memories such as MRAM, ReRAM, or PCM
• Experience developing Radiation Tolerant Layouts
• Track record of publications and patents related to memory design layout

Responsibilities

• Developing high density memory chip custom layout
• Including shared operational circuitry along with at pitch line drivers
• All phases of chip design layout to be included: From architecture definition, density and performance optimization, final verification up to and including tape out
• Running and Debugging Physical Verification flows including DRC, LVS, ERC and Antenna Checks
• Minimize parasitic resistance and capacitance (R and C) in critical paths to meet timing and power consumption specifications
• Comprehend and address reliability engineering issues such as electromigration, IR Drop and Design For Manufacturing robustness
• Coordination of a Split-Fab Design and Development between WD (for Memory Array Layers) and a CMOS Foundry (for Operational Circuitry)
• Developing and Harmonizing CMOS Foundry wafer requirements to allow for continued processing of Memory Array layers in WD’s Fabrication Line
• Development of EDA Tool Design Rules for WD’s Memory Array Layers
• Defining and executing the split-fab tape out flow

Benefits

• paid vacation time
• paid sick leave
• medical/dental/vision insurance
• life, accident and disability insurance
• tax-advantaged flexible spending and health savings accounts
• employee assistance program
• other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity
• tuition reimbursement
• transit
• the Applause Program
• employee stock purchase plan
• the Western Digital Savings 401(k) Plan

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level