Low-Power SoC Physical Design Engineer (Digital)
About The Position
WaveWorks is seeking a Digital Backend Implementation Engineering Contractor to join our Core Platform Engineering team. In this role, you will drive physical implementation of low-power digital designs for a wireless SoC, from RTL handoff through signoff. You’ll focus on synthesis, place & route, clocking, and power implementation, working closely with architecture, RTL, verification, and embedded/software teams to deliver robust, manufacturable silicon that meets aggressive power, performance, and area targets. With our unique technology, WaveWorks is positioned to meet the needs of a plethora of applications of wireless connectivity that are not well served by conventional wireless solutions. Join us as we work to capture this opportunity and become a significant force in wireless.
Requirements
- BS/MS/PhD in Electrical Engineering, Computer Engineering, or equivalent experience.
- 3+ years of experience in digital backend implementation for ASICs or SoCs.
- Strong hands-on experience with synthesis and place & route tools for advanced nodes.
- Deep understanding of low-power digital design and implementation techniques.
- Practical experience implementing multi-power-domain systems using UPF.
- Strong background in clock tree synthesis, optimization, and debugging.
- Proficiency in timing analysis and closure across multiple modes, corners, and voltage domains.
- Solid scripting skills (Tcl, Python, bash) for flow automation and analysis.
- Ability to debug and root-cause complex physical implementation issues.
Nice To Haves
- Experience with ultra-low-power or energy-constrained SoCs (IoT, wireless, battery-powered systems).
- Experience working with multi-voltage, multi-frequency, and power-gated architectures.
- Familiarity with physical design considerations for RF-adjacent or mixed-signal SoCs.
- Experience influencing RTL or architectural decisions to improve power, timing, or routability.
- Experience with signoff power analysis, IR/EM analysis, and silicon correlation.
- Experience collaborating across design, verification, and firmware teams through tapeout and bring-up.
Responsibilities
- Own digital backend implementation flows from synthesis through place & route and signoff for IP blocks and top-level SoCs.
- Implement and optimize multi-power-domain designs using UPF, including power gating, retention, isolation, and level shifters.
- Drive clock tree synthesis and optimization across complex multi-clock designs, balancing power, skew, latency, and robustness.
- Close timing, power, and area across all modes and corners, with particular emphasis on ultra-low-power (microwatt-class) operation.
- Analyze and resolve implementation issues related to congestion, routing, IR drop, EM, noise, and clocking.
- Collaborate closely with RTL, verification, and architecture teams to influence microarchitecture and coding styles for low-power and physical feasibility.
- Develop, maintain, and improve backend flows, scripts, and automation (Tcl/Python) for repeatable, scalable implementation.
- Support signoff activities including STA, power analysis, DRC/LVS handoff, and tapeout readiness.
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What This Job Offers
Career Level
Mid Level
Education Level
Ph.D. or professional degree
Number of Employees
1-10 employees
