The position involves designing adaptive power management controllers, on-chip sensor controllers, and digital power meters. Responsibilities include performing RTL design, simulation, synthesis, timing analysis, lint checks, clock domain crossing checks, conformal low power checks, and formal verification for IP blocks. The role requires close collaboration with the technology/circuit design team to finalize IP block specifications and with the verification/physical design team to complete IP design implementation. Additionally, the candidate will support the SoC team in integrating low power/power management IP solutions into wireless SoC chips and front-end design flows, and work with the system/software/test team to enable low power and functional safety features in automotive SoC products. The role also includes creating and enhancing low power methodologies throughout the design cycle, analyzing the impact of new methodologies, providing feedback for low-power chip and system architecture, and performing block and chip-level power analysis.