Low Power ASIC Engineer - New College Grad 2026

Nvidia-posted about 1 month ago
Full-time • Entry Level
Santa Clara, CA
5,001-10,000 employees
Computer and Electronic Product Manufacturing
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Today, NVIDIA is tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Come join the team and see how we can make a lasting impact on the world! We are now looking for an Low Power Design/Verification ASIC Engineer - New College Grad 2026. We continue to rapidly grow the research and development of energy-efficient GPU and SOC architectures. We are continually innovating in creative and unrivaled ways to improve our ability to deliver exceptional perf/watt solutions in a wide range of sectors. Come join NVIDIAs Low Power DV team to develop state of the art GPUs to power AI, Automotive, GeForce, and Mobile products.

  • Working very closely with Low Power Architecture, Design, and Software teams to understand next generation features.
  • Responsible for architecting/developing testbench, infrastructure, and testplans to verify various power management solutions for NVIDIA products.
  • You will have the opportunity bring creative ideas that help improve power-aware DV methodologies, as well as influence EDA vendors to improve our simulation and debug efficiencies.
  • Pursuing or recently completed a BS, MS or PhD in Electrical or Computer Engineering, or equivalent experience.
  • You have an understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS) etc.
  • Good understanding of processor architecture (GPU is a plus), and related power management design/DV techniques.
  • Must be experienced with Incisive Low-Power or Synopsys VCS NLP
  • Strong debug skills and experience with Verdi is needed
  • Must be fluent in Verilog, SystemVerilog, and understanding of UVM.
  • Prior knowledge of Low Power Architecture, Low Power CV, and deep learning
  • Good understanding of power intent in UPF format is a plus
  • A strong background in Low Power architectures or verification is a plus.
  • Scripting abilities in Python or PERL is a plus and knowledge of C or C++ is a plus
  • Experience writing or maintaining the script or Makefile that builds the simulation program is a plus
  • You will also be eligible for equity and benefits.
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