Link Layer architect

Marvell Technology • Santa Clara, CA

10d

About The Position

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell’s Compute and Custom Solutions organization (CCS) is looking for a talented senior ASIC link layer architect to join our architecture team. This team acts as the central technical interface to our datacenter clients. It is responsible for the overall technology choice, silicon partitioning strategy, IP definition and selection and architectural guidance of datacenter products (SmartNIC, servers, AI accelerators and switches, mainly) for the main hyperscalers and companies worldwide. We actively participate in the definition of next generation datacenter products with our clients and respond to their ASIC RFQs. Role spans engagement with both customers and internal technology teams to define the best solution to the custom product needs and includes all functions required to build, test and manufacture an advanced custom silicon System in a Package. What You Can Expect We are seeking a senior Link Layer Architect to own the end-to-end architecture of link layer solutions across high-speed interconnect protocols including Ethernet, Custom link-layers and Die-to-Die (D2D) interfaces. This role offers the opportunity to shape the future of high-speed interconnect technologies at Marvell, engaging with customers to enable next-generation computing and communication systems as an integral part of the Custom Solutions Architecture team.

Requirements

• Extensive experience (typically 10+ years) in link-layer design and architecture
• Deep understanding of Ethernet link layer IEEE 802.3 (100G and 200G)
• Strong knowledge of link layer protocols, error detection/correction, and reliability mechanisms
• Experience with FEC implementations (Reed-Solomon, Hamming, BCH, etc.)
• Understanding of link training, equalization, and physical layer interaction
• Proven track record of defining successful system architectures
• Experience guiding RTL design and verification, including design reviews and architectural trade-offs (hands-on experience a plus)
• Understanding of SerDes/PHY interfaces and requirements
• Excellent written and verbal communication skills
• Ability to present complex technical concepts to diverse audiences
• Experience leading cross-functional technical initiatives
• Strong problem-solving and analytical capabilities

Nice To Haves

• MS or PhD in Electrical Engineering, Computer Engineering, or related field
• Experience with chiplet architectures and advanced packaging
• Prior involvement in industry standards organizations
• Knowledge of network protocol stacks and system architecture

Responsibilities

• Define and develop link layer architectures for various high-speed interconnects (Ethernet and custom link-layers)
• Drive link layer architecture in the context of full-system performance, power, reliability and scalability goals
• Create architectural specifications and design documents for link layer protocols and implementations
• Drive technical decisions on link layer features including error correction, flow control, retry mechanisms, and data integrity
• Evaluate and recommend new link layer technologies and standards for next-generation products and custom solutions
• Lead architecture reviews and provide technical guidance to cross-functional teams
• Define interfaces between link layer, transaction layer, and physical layer
• Optimize link efficiency, latency, and bandwidth utilization
• Stay current with emerging link layer standards and technologies
• Contribute to specification development and review
• Ensure compliance with industry standards and specifications
• Engage directly with customers on architecture discussions, including requirements definition, architectural alignment, and design trade-offs
• Work closely with PHY architects, system architects, and ASIC design teams
• Partner with verification teams to define test plans and coverage strategies
• Support hardware bring-up and validation teams with technical expertise
• Research and evaluate new link layer technologies and approaches
• Develop proof-of-concept implementations for novel link layer features
• Create reusable IP blocks and architectural frameworks
• Drive continuous improvement in link layer performance and reliability
• Create comprehensive architecture specifications and design documentation
• Develop datasheets, integration guides, and reference designs
• Present technical concepts to internal teams and external customers
• Mentor engineers and share link layer expertise across the organization

Benefits

• employee stock purchase plan with a 2-year look back
• family support programs to help balance work and home life
• robust mental health resources to prioritize emotional well-being
• recognition and service awards to celebrate contributions and milestones

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 1,001-5,000 employees