EE 301: Digital Systems Design with HDL Position: Lecturer - Academic Year Semester: Spring 2026 Days/Times: Varies multiple sections Modality: In-person College: College of Science, Technology, Engineering, and Mathematics Department: Electrical & Computer Engineering The Electrical & Computer Engineering Department at California State University San Marcos seeks a part-time lecturer for Spring 2026 to teach EE 301: Digital Systems Design with HDL. The successful candidate will collaborate with the lecture instructor and teach the laboratory portion of the course. Course Description: Covers advanced topics in digital systems design. Utilizes register-transfer level tools for logic synthesis, simulation, and the implementation of digital circuits in field-programmable gate arrays (FPGAs). Includes the basic building blocks of FPGA programming, architecture, best design practices, error-free design, and optimizations of finite state machines and logic circuit performance. Incorporates top-down design using a hardware description language (such as VHDL), test bench development, and implementation of advanced digital design systems in the laboratory component.