Lead Verification Engineer

Neurophos • Austin, TX

8h • Onsite

About The Position

We are developing an ultra-high-performance, energy-efficient photonic AI inference system. We’re transforming AI computation with the first-ever metamaterial-based optical processing unit (OPU).
As AI adoption accelerates, data centers face significant power and scalability challenges. Traditional solutions are struggling to keep up, leading to rapidly rising energy consumption and costs. We’re solving both problems with an OPU that integrates over one million micron-scale optical processing components on a single chip. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving large-scale AI inference performance.
We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years.
Join us and shape the future of optical computing!
Location: Austin, TX. Full-time onsite position.
Position Overview:
We are seeking a highly skilled and experienced ASIC Verification Lead to join our engineering team. In this role, you will take ownership of the verification strategy and execution for complex SoCs, ensuring the functional integrity of our silicon through advanced methodologies and automated flows. You will be a key driver in architectural decisions and the evolution of our verification infrastructure.

Requirements

• 10+ years of industry experience in verification, ideally leading efforts for verification of complex ASICs in a startup environment.
• Mastery of SystemVerilog, SystemC, and expert-level experience with the UVM methodology.
• Proven experience with SystemC for high-level modeling and seamless integration into RTL verification environments.
• Strong C coding skills specifically for ARM and RISC-V architectures to support firmware-driven verification.
• Deep experience with Cadence tool suites and the ability to script (Python, Bash, or Perl) for CI/CD integration and flow automation.
• Technical depth in PCIe protocol verification, including knowledge of clocking architectures and jitter requirements.
• Experience in running, debugging gate-level simulations with timing (SDF), and managing CDC/Lint tools

Nice To Haves

• Experience with Analog Mixed-Signal (AMS) verification environments and Real Number Modeling (RNM).
• Formal, assertion-based verification experience is highly desirable
• Familiarity with hardware-assisted verification platforms (e.g., Palladium, ZeBu, or HAPS).

Responsibilities

• Define and execute comprehensive verification plans, including feature extraction, coverage metrics, and tracking mechanisms.
• Architect and develop scalable UVM-based testbenches and constrained-random environments, as well as targeted SystemVerilog C-based testbenches used for HW/SW co-design.
• Integrate and verify SystemC models within the verification flow to support architectural exploration and early software development.
• Maintain and enhance the verification flow using Cadence EDA tools (e.g., Xcelium, JasperGold). Develop CI/CD scripts to automate regressions and improve turnaround time.
• Development of git based CI/CD tools and quality tests using GitHub Actions.
• Verification management: Manage local and external contractors, using coverage and assertion-based metrics.
• Perform functional verification of processor sub-systems using SystemVerilog and C-based directed testing.
• Integrate FPGA platforms (emulation or prototyping) into the verification flow to accelerate software development and system-level validation.
• Lead sign-off activities, including gate-level simulations (GLS) with SDF annotations, Lint, and Clock Domain Crossing (CDC) analysis.
• Drive verification of high-speed protocols, with a focus on PCIe interface logic and protocol compliance.
• Develop and verify AMS and SystemVerilog models for in-house analog designs.

Benefits

• A pivotal role in an innovative startup redefining the future of AI hardware.
• A collaborative and intellectually stimulating work environment.
• Competitive compensation package including equity participation.
• Comprehensive benefits, including health, dental, and vision insurance.
• Opportunities for career growth and future team leadership.
• Access to cutting-edge technology and state-of-the-art facilities.
• Opportunity to publish research and contribute to the field of efficient AI inference.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed