Lead Technology Node Owner

Advanced Micro Devices, Inc•Austin, TX

7h•Onsite

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Technology Node Owner THE ROLE: AMD is seeking an accomplished Principal Member of Technical Staff (PMTS) to serve as Technology Node Owner within the Silicon Technology (SiTech) organization. This highly visible technical leadership role is central to advancing AMD’s leading‑edge semiconductor technologies and directly enabling the company’s long‑term product roadmap. The position is based in Austin, Texas, and offers the opportunity to influence cutting‑edge process technologies in close collaboration with world‑class foundry partners. KEY RESPONSIBILITIES: As the Technology Node Owner, the successful candidate will provide technical leadership across the full lifecycle of advanced silicon technology development, from early definition through product ramp. Core responsibilities include:

Requirements

Strong foundational knowledge of semiconductor device physics and advanced fabrication processes such as FinFET, GAA, or next-generation device architectures.
Extensive experience with New Product Introduction (NPI) for advanced technology nodes.
Solid understanding of IC design fundamentals and the key factors affecting model‑to‑hardware correlation.
Demonstrated expertise with PDK components, including design rule manuals, SPICE models, and related design enablement infrastructure.
Familiarity with technology and product reliability, including CPI (Chip‑Package Interaction) considerations.
Experience with process SPC control, statistical data analysis, and interpretation.
Outstanding written and verbal communication abilities.
Strong program and project management skills, with the ability to coordinate complex, multidisciplinary efforts across multiple organizations and stakeholders.
Master’s degree or higher in Electrical Engineering or a related technical field with proven industry experience

Nice To Haves

Exposure to SRAM and analog design methodologies is highly desirable.
Ph.D. may be considered in lieu of some industry experience.

Responsibilities

Defining, developing, and driving foundry technology capabilities to align with AMD’s product strategy and aggressive roadmap requirements.
Partnering closely with leading semiconductor foundries to establish ambitious yet achievable technology targets and to extend performance through Design‑Technology Co‑Optimization (DTCO) beyond intrinsic foundry capabilities.
Assessing technology and manufacturing readiness through well‑defined milestones, ensuring timely execution and risk mitigation.
Analyzing complex data sets from foundry partners to inform critical technology decisions and ensure alignment with product goals.
Leading cross‑functional engagement with design, reliability, packaging, and product engineering teams to ensure technology readiness meets stringent PPAYQ (Performance, Power, Area, Yield, and Quality) requirements.
Ensuring delivery of robust design enablement collateral, including early technology definitions, PDK components, and modeling accuracy necessary for successful product development and ramp‑up.