Lead STA & Implementation Engineer

Qualcomm•Santa Clara, CA

About The Position

Qualcomm-Atheros, a.k.a. QCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team. The role involves ownership and leading Static timing closure and synthesis for complex low-power WiFi SoCs and sub-systems. Qualcomm’s Wi‑Fi SoC organization is seeking an experienced and highly skilled Static Timing Analysis (STA) and Synthesis Engineer to contribute to the development of next‑generation connectivity chipsets. This role focuses on driving timing‑critical implementation for high‑performance, low‑power Wi‑Fi solutions used across mobile, Access point (WIN), XR, automotive, and IoT platforms. You will collaborate closely with Architecture, RTL design, Design verification, DFT, and physical design teams to deliver high‑quality silicon on aggressive schedules. The responsibilities include the following Timing Analysis: Lead full-chip and sub-system level Static Timing Analysis (STA) and timing closure for both pre-layout and post-layout phases. Lead and drive full‑chip and block‑level STA using Prime Time or equivalent tools. Analyze timing bottlenecks and propose architectural or micro‑architectural improvements Support ECO flows for late‑stage timing fixes and functional corrections. Synthesis & Implementation: Perform synthesis (including low power), formal verification (LEC), and low-power checks for complex SoCs, sub-systems, and cores. Validate synthesis QoR and ensure clean handoff to physical design. Develop, validate, and maintain SDC constraints. Balance Power, Performance, and Area (PPA) constraints during implementation. Perform functional ECOs including conformal ECOs Methodology: Develop AI‑driven flows using TCL, Perl, and Python scripts to automate and enhance efficiency across STA, synthesis, timing‑constraint development, ECO implementation, and low‑power verification flows.

Requirements

7–10+ years of experience in ASIC/SoC STA, synthesis (including low power), timing constraint development, Low power checks and functional ECO implementation.
Deep knowledge of Static Timing Analysis (STA), Synthesis and timing constraints.
Experience with Multi Mode Multi Corner (MMMC) timing closure, OCV/AOCV/POCV, and advanced technology nodes.
Experience with timing closure sign off requirements.
Experience in Logical Equivalence Checking (LEC) (RTL-to-Netlist and Netlist-to-Netlist).
Understanding of SOC clocking and reset methodology and implementation.
Strong scripting skills in TCL and Perl.
Experience with Low implementation techniques and design checks (multi-voltage designs, UPF).
Hands‑on experience with: Synopsys Prime Time Synopsys Design Compiler / Cadence Genus

Nice To Haves

Familiarity with Low power design, Bus implementation (AXI/AHB) and Clock Domain Crossing (CDC)
Familiarity with Wi‑Fi, Bluetooth, or other wireless SoC architectures.
Familiarity with peripheral interfaces (PCIe. SDIO, and USB).
Exposure to physical design flows
Scripting skills using Python.
Exposure to power estimation using PrimePower (PTPX)
Conformal/Formality for logic equivalence checking

Responsibilities

Lead full-chip and sub-system level Static Timing Analysis (STA) and timing closure for both pre-layout and post-layout phases.
Lead and drive full‑chip and block‑level STA using Prime Time or equivalent tools.
Analyze timing bottlenecks and propose architectural or micro‑architectural improvements
Support ECO flows for late‑stage timing fixes and functional corrections.
Perform synthesis (including low power), formal verification (LEC), and low-power checks for complex SoCs, sub-systems, and cores.
Validate synthesis QoR and ensure clean handoff to physical design.
Develop, validate, and maintain SDC constraints.
Balance Power, Performance, and Area (PPA) constraints during implementation.
Perform functional ECOs including conformal ECOs
Develop AI‑driven flows using TCL, Perl, and Python scripts to automate and enhance efficiency across STA, synthesis, timing‑constraint development, ECO implementation, and low‑power verification flows.