Lead RTL Design Engineer

Cerebras Systems • Sunnyvale, CA

39d • $175,000 - $275,000 • Hybrid

About The Position

As a lead front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. The role also requires close collaboration and management of external ASIC vendor. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.

Requirements

• Master’s degree in Computer Science, Electrical Engineering, or equivalent.
• Can work in a hybrid work environment.
• 10+ years of experience in delivering complex, high performance high quality RTL designs.
• Experience with Front End Chip integration and third-party IP integration.
• Demonstrated experience in networking, high-performance computing, machine learning or related fields.
• Proven track record of multiple silicon success.
• Experience collaborating and managing external vendors.
• Experience with designing/integrating high speed IO.
• Networking stack experience including TCP/IP, RDMA and Ethernet.
• Knowledge of PCIe, CPU interfaces and Serdes technology.
• Working knowledge of scripting tools : Python, TCL.

Nice To Haves

• Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.

Responsibilities

• Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
• Managing external ASIC vendor through product development cycle.
• Work closely with PD team members for design closure to meet PPA goals.
• Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
• Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
• Debug silicon-level functional, timing, and power issues during bring up.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 251-500 employees