Astera Labs Inc. is a fabless semiconductor company that develops purpose-built connectivity solutions to remove performance bottlenecks in compute-intensive workloads such as artificial intelligence and machine learning. To support our rapid growth, we are hiring a Lead IC Package Designer with extensive experience in complex ASIC package design using Cadence APD. Background in SI/PI is a plus. As an Astera Labs Lead Package Design Engineer, you will take ownership of package design and layout for Astera Labs’ portfolio of connectivity products deployed by the world’s leading cloud service providers and server/networking OEMs. You will be responsible for driving package substrate design from definition to tape-out, including performance optimization, design for manufacturing, and sign-off verification. You will also provide technical guidance within the package design team: mentoring junior designers, guiding best practices in APD, reviewing design work for quality and consistency, and working closely with SI/PI, product engineering, and hardware teams to ensure first-pass success. You will also help shape design flows, champion productivity improvements, and represent package design expertise in cross-functional discussions.
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Job Type
Full-time
Career Level
Senior
Education Level
Bachelor's degree
Number of Employees
251-500 employees