Lead Package Design Engineer

Astera LabsSan Jose, CA
98d$175,750 - $230,000

About The Position

Astera Labs Inc. is a fabless semiconductor company that develops purpose-built connectivity solutions to remove performance bottlenecks in compute-intensive workloads such as artificial intelligence and machine learning. To support our rapid growth, we are hiring a Lead IC Package Designer with extensive experience in complex ASIC package design using Cadence APD. Background in SI/PI is a plus. As an Astera Labs Lead Package Design Engineer, you will take ownership of package design and layout for Astera Labs’ portfolio of connectivity products deployed by the world’s leading cloud service providers and server/networking OEMs. You will be responsible for driving package substrate design from definition to tape-out, including performance optimization, design for manufacturing, and sign-off verification. You will also provide technical guidance within the package design team: mentoring junior designers, guiding best practices in APD, reviewing design work for quality and consistency, and working closely with SI/PI, product engineering, and hardware teams to ensure first-pass success. You will also help shape design flows, champion productivity improvements, and represent package design expertise in cross-functional discussions.

Requirements

  • BS/MS in Engineering (Electrical, Mechanical, Materials Science, Physics, or related field).
  • 6+ years of experience in Cadence APD/SiP with a track record of independently designing and releasing FCBGA/FCCSP packages from concept to tape-out.
  • Proven experience leading package design efforts and mentoring other designers.
  • Deep understanding of BGA substrate technologies, stackups, design rules, and assembly processes.
  • Familiarity with package reliability, SI/PI, and design sign-off methodologies.
  • Strong collaboration and communication skills.

Nice To Haves

  • Multi-chip, interposer, 2.5D or heterogeneous package design experience.
  • Proficiency in scripting languages for design and reporting automation.

Responsibilities

  • Take ownership of package design and layout for connectivity products.
  • Drive package substrate design from definition to tape-out.
  • Optimize performance and ensure design for manufacturing.
  • Conduct sign-off verification of designs.
  • Mentor junior designers and guide best practices in APD.
  • Review design work for quality and consistency.
  • Collaborate with SI/PI, product engineering, and hardware teams for first-pass success.
  • Shape design flows and champion productivity improvements.
  • Represent package design expertise in cross-functional discussions.

Benefits

  • Base salary range of $175,750.00 USD – $230,000.00 USD based on location and experience.
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