Lead Micro-Architect, Memory Controller

Samsung Electronics•Austin, TX

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! We are seeking a highly skilled Lead Memory Controller Micro-Architect to lead the design and development of Samsung's advanced memory controller (LPDDR5, LPDDR6, PIM, and beyond (DDR5, GDDR7, HBM4). By being at the forefront of the full technology development cycle, you will have the opportunity to further develop your expertise in memory controllers, pushing the boundaries of what is possible and redefining the future of memory technology. You will assume ownership and exert significant influence over the entire memory-controller micro-architecture, including RTL design and performance/power optimization. You will translate innovative concepts into cutting-edge, next-generation memory technologies that drive Samsung's leadership in the field. You are the domain expert in technical areas with strong engineering foundation and RTL design experience, driving micro-architecture, RTL design, debug, and timing closure for custom memory controllers. You're passionate about microarchitecture development, from high-level exploration to delivering high-quality RTL on schedule, meeting performance, power, and area (PPA) goals. You ensure design quality through LINT, CDC, ECO flows, power analysis, and other methodologies. You collaborate with cross-functional teams to ensure design functionality, achieve PPA goals, and resolve implementation challenges in a fast-paced environment. You take ownership of deliverables by adhering to JEDEC standards, collaborating on SOC IP delivery, and applying knowledge of DDR PHY to ensure timely and accurate results.

Requirements

20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD
Proven experience in memory controller micro-architecture and RTL design, owning all sub-blocks of custom memory controller designs.
Deep expertise in multiple memory technologies, such as LPDDR4/5/6, PIM, DDR, GDDR, and HBM.
Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY.
Demonstrated success in driving architecture through RTL design for high-performance digital systems.
Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO.
Proficiency in scripting languages (Perl, Python) to support design and automation.
Strong communication and collaboration skills; Ability to navigate ambiguity in a fast-paced, global team environment.

Nice To Haves

Familiarity with interface protocols (AMBA, AXI, ACE) is desired.
Knowledge of AES, ECC, and RAS features is preferred.
Self-driven, curious, and passionate about logic design and innovation.

Responsibilities

Assume ownership and exert significant influence over the entire memory-controller micro-architecture, including RTL design and performance/power optimization.
Translate innovative concepts into cutting-edge, next-generation memory technologies that drive Samsung's leadership in the field.
Drive micro-architecture, RTL design, debug, and timing closure for custom memory controllers.
Ensure design quality through LINT, CDC, ECO flows, power analysis, and other methodologies.
Collaborate with cross-functional teams to ensure design functionality, achieve PPA goals, and resolve implementation challenges in a fast-paced environment.
Take ownership of deliverables by adhering to JEDEC standards, collaborating on SOC IP delivery, and applying knowledge of DDR PHY to ensure timely and accurate results.