Lead Memory Controller Architect

Samsung•San Jose, CA

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities We are seeking a highly skilled Memory Controller Architect to own the design and development of Samsung's advanced custom memory controller IP. By being at the forefront of the full technology development cycle, you will have the opportunity to further develop your expertise in memory controllers, pushing the boundaries of what is possible and redefining the future of memory technology. You will lead a team and exert significant influence over the entire memory controller architecture and micro-architecture, including RTL design and performance/power optimization. You will translate innovative concepts into cutting-edge, next-generation memory technologies, including the latest enhancements in DDR, LPDDR, PIM, GDDR, and HBM, that drive Samsung's leadership in the field. You are the domain expert in technical areas with a strong engineering foundation and RTL design experience, driving architecture, micro-architecture, RTL design, debug, and timing closure for our custom memory controller. You ensure design quality through LINT, CDC, ECO flows, power analysis, and other methodologies. You collaborate with cross-functional teams to ensure design functionality, achieve PPA goals, and resolve implementation challenges in a fast-paced environment. You take ownership of deliverables by adhering to JEDEC standards, collaborating on SOC IP delivery, and applying knowledge of DDR PHY to ensure timely and accurate results. Skills and Qualifications 20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD. Proven experience in memory controller architecture and micro-architecture, leading a team through the entire development lifecycle. Deep expertise in multiple memory technologies, such as DDR, LPDDR, PIM, GDDR, and HBM. Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY. Demonstrated success in driving architecture through RTL design for high-performance digital systems. Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO. Proficiency in scripting languages (Perl, Python) to support design and automation. Strong communication and collaboration skills with the ability to navigate ambiguity in a fast-paced, global team environment. Familiarity with interface protocols (AMBA, AXI, ACE, CHI) is desired. Knowledge of AES, ECC, and RAS features is preferred. Self-driven, curious, and passionate about logic design and innovation. Our Team Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem. With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments. Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture. Total Rewards At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $221,700 and $364,800. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA). Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance. Additionally, this role might be eligible to participate in long term incentive plan and relocation.

Requirements

20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD.
Proven experience in memory controller architecture and micro-architecture, leading a team through the entire development lifecycle.
Deep expertise in multiple memory technologies, such as DDR, LPDDR, PIM, GDDR, and HBM.
Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY.
Demonstrated success in driving architecture through RTL design for high-performance digital systems.
Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO.
Proficiency in scripting languages (Perl, Python) to support design and automation.
Strong communication and collaboration skills with the ability to navigate ambiguity in a fast-paced, global team environment.

Nice To Haves

Familiarity with interface protocols (AMBA, AXI, ACE, CHI) is desired.
Knowledge of AES, ECC, and RAS features is preferred.
Self-driven, curious, and passionate about logic design and innovation.

Responsibilities

Lead a team and exert significant influence over the entire memory controller architecture and micro-architecture, including RTL design and performance/power optimization.
Translate innovative concepts into cutting-edge, next-generation memory technologies, including the latest enhancements in DDR, LPDDR, PIM, GDDR, and HBM, that drive Samsung's leadership in the field.
Drive architecture, micro-architecture, RTL design, debug, and timing closure for our custom memory controller.
Ensure design quality through LINT, CDC, ECO flows, power analysis, and other methodologies.
Collaborate with cross-functional teams to ensure design functionality, achieve PPA goals, and resolve implementation challenges in a fast-paced environment.
Take ownership of deliverables by adhering to JEDEC standards, collaborating on SOC IP delivery, and applying knowledge of DDR PHY to ensure timely and accurate results.