Lead High-Speed PCB Layout Engineer

Array Labs • Palo Alto, CA

3d • $160,000 - $200,000

About The Position

As a Lead High-Speed PCB Layout Engineer, you will own the physical implementation of Array’s high-speed digital and mixed-signal electronics in Altium, translating schematics and performance requirements into layouts and functional designs. Your work will include component placement, constraint-driven routing, stack-up definition, return path and reference plane strategy, and partitioning between sensitive mixed-signal domains and high-speed digital interfaces.

You will partner closely with electrical design, firmware, mechanical, and test engineers to drive layout constraints, reviews, and manufacturing releases. The boards you ship will directly determine signal integrity, power integrity, noise performance, and overall system reliability in the lab and on orbit.

Requirements

• B.S. in Electrical Engineering, or a related field with 8+ years of relevant experience
• Experience in PCB layout, fabrication, and release of high-speed digital and mixed-signal electronics
• Excellent teamwork and communication skills
• Learns new concepts rapidly, completely, and in a self-directed manner
• High levels of self-motivation and personal accountability
• Ability to work in a fast-paced environment under significant time constraints

Nice To Haves

• Experience designing high-speed digital and mixed-signal PCB layouts including constraint-driven routing, impedance control, and length matching
• Comfort with Altium Designer for complex layout and clean manufacturing outputs; familiarity with Allegro and/or OrCAD
• Experience developing PCB stack-ups and layout constraints for high-speed interfaces and dense, high-performance boards
• A strong intuition for layout-driven SI/PI behavior, including return paths, reference plane strategy, via transitions, and noise coupling between domains
• Experience working closely with electrical design engineers to translate schematic intent into layouts that work on the first spin
• Experience with manufacturing release, DFM/DFT considerations, and collaborating with fabrication and assembly partners
• Experience supporting lab bring-up and debug alongside design and test engineers, including investigating SI/PI issues observed on hardware
• Familiarity with SI/PI analysis workflows and tools such as Ansys SIwave, Keysight Power Analyzer, HyperLynx, or Sigrity
• Experience taking high-performance hardware from prototype through qualification and environmental testing

Responsibilities

• Own high-speed PCB layout from initial placement through manufacturing release in Altium
• Define and implement stack-ups, impedance targets, length-matching constraints, and reference plane/return-path strategies for high-speed interfaces
• Translate schematic intent into layouts that meet signal integrity and power integrity requirements across mixed-signal and digital domains
• Partner with electrical design, firmware, mechanical, and test engineers to develop layout constraints, run reviews, and de-risk first-pass success
• Drive DFM/DFT considerations with fabrication and assembly partners, including documentation and release artifacts

Benefits

• competitive pay
• generous equity
• high flexibility between salary and equity-based compensation

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level