Lead Graphics Memory Power Architect, Performance Optimization

Advanced Micro Devices • Santa Clara, CA

78d • Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences - from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. As a Lead Graphics Memory Power Architect, Performance Optimization, you will lead architectural power optimization efforts across memory-related components in AMD's next-generation GPU and APU products. You will be part of a cross-functional architecture team focused on delivering industry-leading performance-per-watt (PPA) across compute, gaming, and AI workloads. This role is central to AMD's 'shift-left' initiative-embedding power efficiency early in the architecture phase to reduce downstream design costs and improve silicon efficiency.

Requirements

• Strong understanding of memory architecture: caches (L1/L2), DRAM interfaces, coherency, compression, and selective coherence.
• Experience with power modeling tools and methodologies.
• Familiarity with GPU architecture and shader workloads.
• Ability to analyze RTL and system-level power behavior.
• Proficiency in scripting and modeling languages (Python, C, RTL).
• Excellent communication and collaboration skills across time zones and disciplines.

Nice To Haves

• A Master's or PhD in Computer Engineering or Electrical Engineering is preferred, along with mastery of logic and circuit design principles, and hardware methods relevant to complex systems and platforms.

Responsibilities

• Architect and implement power optimization strategies for memory subsystems including cache hierarchies, compression engines, coherency protocols, and interconnects.
• Collaborate with RTL, PD, software, and modeling teams to define and validate architectural features that improve PPA.
• Analyze game traces and real-world workloads to identify power hotspots and propose mitigation strategies.
• Develop and maintain power models for memory subsystems and validate against silicon measurements.
• Lead architectural reviews and provide technical guidance on Di/Dt mitigation, clock gating, power gating, and wake-up latency.
• Contribute to architectural specifications and programming guides, including power chapters.
• Engage with internal stakeholders and external partners to align on power goals and trade-offs.
• Guide HW Design teams in evaluating and improving power efficiency of their implementations.

Benefits

• AMD benefits at a glance.

What This Job Offers

• Job Type: Full-time
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Master's degree
• Number of Employees: 5,001-10,000 employees