Lead Design Verification Engineer

Intel • Santa Clara, CA

28d • Onsite

About The Position

We are seeking a highly accomplished Silicon Design Verification Architect to define, architect, and deliver end‑to‑end verification strategies for complex IPs, subsystems, and SoCs. In this role, you will lead the development of scalable, reusable verification infrastructures and methodologies, drive functional and security coverage closure, and ensure first‑pass silicon success across pre‑ and post‑silicon validation. This is a hands‑on technical leadership role requiring deep expertise in UVM‑based simulation, formal and multimodal verification, and verification infrastructure architecture, as well as close collaboration with design, architecture, software, and post‑silicon teams.

Requirements

• BS or MS in Electrical Engineering, Computer Science, or a related field, with 10+ years of industry experience in silicon design verification.
• 8+ years of experience across IP‑level, subsystem‑level, and SoC‑level verification, with demonstrated ownership of complex verification architectures.
• Strong expertise in simulation‑based verification methodologies, including UVM, assertion-based verification, co-simulation, and low-power verification.
• Advanced coding skills in SystemVerilog/UVM.
• Excellent communication, technical writing, and organizational skills, with a strong record of cross‑functional collaboration.

Nice To Haves

• Proven hands‑on experience developing highly configurable and reusable Verification IP (VIP) such as AMBA, PCIe, HBM, LPDDR, or similar complex protocols.
• Advanced coding skills in SystemVerilog/UVM, C/C++, Python, and scripting/build systems such as Make, CMake, or Bazel.
• Demonstrated history of delivering robust, scalable verification tools and infrastructure that enable high‑quality, on‑time silicon.

Responsibilities

• Define and own the verification architecture and strategy for IPs, subsystems, and full SoCs, ensuring optimal tradeoffs between completeness, performance, reuse, and scalability.
• Architect, implement, and maintain advanced UVM and formal‑based verification environments, including configurable, reusable testbenches and verification components.
• Design and integrate block‑level testbenches into chip‑level UVM environments, executing and validating complex IP and SoC integrations.
• Develop comprehensive test strategies, testbench architectures, and verification plans aligned with design specifications, coverage goals, and silicon milestones.
• Lead random and constrained‑random test generation, functional simulation, and regression strategies to uncover design gaps and corner‑case defects.
• Drive coverage analysis, failure root-cause analysis, and coverage closure, ensuring measurable verification completeness and signoff readiness.
• Develop and execute low‑power and security validation strategies, including definition of security coverage models and deployment of security‑focused verification infrastructure.
• Collaborate closely with design, architecture, analog, software, and post‑silicon teams to align verification intent across the full product lifecycle.
• Support post‑silicon validation and debug, leveraging pre‑silicon environments and collateral to accelerate issue isolation and resolution.
• Mentor and influence verification engineers across teams through best practices, design reviews, and technical leadership.

Benefits

• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel .

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees